One example of frequency synthesizer is known as a “Flying Adder” frequency synthesis architecture. The architecture is described in “An Architecture of High Performance Frequency and Phase Synthesis”, by Hugh Mair and Liming Xiu; IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, June 2000. Mair and Xiu describe a voltage controlled oscillator (VCO) presenting a VCO input reference signal having thirty-two phases as an input signal to a multiplexer device.
Referring preliminarily to FIG. 1 (which is described below in greater detail), a frequency synthesis section includes a frequency synthesizer multiplexer device that selects one of the thirty-two phases of the VCO input reference signal to present a drive signal VMUX to trigger a toggle flip-flop and generate a frequency output signal CLK having a rising edge and a falling edge. A control word FREQ (a digital word) determines the time (i.e., the number of phases) that should elapse between two adjacent selections of address by the frequency synthesizer multiplexer device. A frequency synthesis register provides and memorizes the extant selection address of the frequency synthesizer multiplexer device. Drive signal VMUX is applied as a clocking signal for the frequency synthesis register. The next subsequent frequency synthesizer multiplexer selection address stored in the frequency synthesis register is the sum of the extant selection address and the control word FREQ.
Additionally, the multiple VCO phases may be programmed to obtain a delay with respect to the input reference signal using a delay synthesis section that includes a delay synthesizer multiplexer device that selects one of the thirty-two phases of the VCO input reference signal to present a drive signal VMUX-D to trigger a toggle flip-flop and generate a delay output signal CLK-D. A control word DELAY (also a digital word) determines the incremental value (i.e., the number of phases) to be added to the frequency synthesizer multiplexer selection address. A delay synthesis register provides and memorizes the extant selection address (frequency address plus the delay shift) for the delay synthesizer multiplexer device. Drive signal VMUX-D is applied as a clocking signal for the delay synthesis register.
A result is that both the drive signals VMUX, VMUX-D have the same frequency that is determined by control word FREQ. However, the rising edge of drive signal VMUX-D is determined by control word DELAY and may therefore differ from the rising edge of drive signal VMUX. If drive signal VMUX (which is always earlier than VMUX-D), is offset with respect to drive signal VMUX-D by an amount less than computation time of the adder summing the two inputs (extant address in the frequency synthesizer multiplexer device and control word DELAY), a timing violation may be produced that will render the apparatus inoperative.
The requirement for using two multiplexing devices and the disparately timed clocking signals for the frequency synthesis register and the delay synthesis register contribute to disadvantages for signal synthesis apparatuses of the type represented in FIG. 1. Among the disadvantages are high part count and consequent large die area required for implementing the circuitry. A further disadvantage is the possible timing violation that may occur because of the disparately timed clocking signals used for the frequency synthesis register and the delay synthesis register.